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memories for graphics systems 16m synchronous graphics ram sgram HYB39S16320TQ-6 hyb39s16320tq-7 hyb39s16320tq-8 version 2.1.00 preliminary information sgram 1.1999
edition 1.1999 this edition was realized using the software system framemaker a . published by siemens ag, bereich halbleiter, marketing- kommunikation, balanstra?e 73, 81541 mnchen ? siemens ag 1999. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens companies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be en- dangered. HYB39S16320TQ-6/-7/-8 revision history: current version 2.1.00 previous version: 1.x.xx page (in previous version) page (in new version) all versions with major number 1 (1.x.xx) are replaced by this version previous version: 2.0.00 30 30 i cc3p in table operating currents changed 32 32 t ah in table ac characteristics changed
synchronous graphics ram sgram HYB39S16320TQ-6 hyb39s16320tq-7 hyb39s16320tq-8 users manual 1.1999
semiconductor group 4 1.1999 HYB39S16320TQ-6 /-7 /-8 overview 1overview the hyb39s16320tq are dual bank synchronous graphics drams (sgram) organized as 2 banks x 256kbit x 32 with built-in graphics features. these synchronous devices achieve high speed data transfer rates up to 166 mhz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. the chip is fabricated with an advanced 64mbit dram process technology. the device is designed to comply with all jedec standards set for synchronous graphics dram products, both electrically and mechanically. ras , cas , we, dsf and cs are pulsed signals which are examined at the positive edge of each externally applied clock. internal chip operating modes are defined by combinations of these signals. a ten bit address bus accepts address data in the conventional ras / cas multiplexing style. ten row address bits (a0-a9) and a bank select ba are strobed with ras. column address bits plus a bank select are strobed with cas. prior to any access operation, the cas latency, burst length and burst sequence must be programmed into the device by address inputs during a mode register set cycle. an auto precharge function may be enabled to provide a self-timed row precharge. this is initiated at the end of the burst sequence. in addition, it features the write per bit, the block write and the masked block write functions. by having a programmable mode register and special mode register, the system can select the best suitable modes to maximize its performance. operating the two memory banks in an interleave fashion allows random access operation to occur at higher rate than is possible with standard drams. a sequential and gapless data rate of up to 166 mhz is possible depending on burst length, cas latency and speed grade of the device. auto refresh (cbr) and self refresh operation are supported. these devices operate with a single 3.3v +/- 0.3v power supply and are available in 100pin tqfp package. ? high performance: ? single pulsed ras interface ? programmable cas latency : 2, 3 ? fully synchronous to positive clock edge ? programmable wrap sequence : sequential or interleave ? programmable burst length: 1, 2, 4, 8 and full page for sequential 1, 2, 4, 8 for interleave -6 -7 -7 -8 unit f ck 166 125 125 125 mhz latency 3 2 3 3 # t ck3 6878ns t ac3 5.5 5.5 5.5 6 ns ? special mode registers ? two color registers ? burst read with single write operation ? block write and write-per-bit capability ? byte controlled by dqm0-3 ? auto precharge and auto refresh modes ? suspend mode and power down mode ? 2k refresh cycles / 32 ms ?t ac = 5.5ns ?t setup / t hold = 2ns / 1ns ? latency 2 @ 125 mhz ? random column address every clk (1-n rule) ? single 3.3v +/- 0.3v power supply ? lvttl compatible inputs and outputs
semiconductor group 5 1.1999 HYB39S16320TQ-6 /-7 /-8 overview 1.1 features ? all signals fully synchronous to the positiv edge of the system clock ? programmable burst lengths: 1, 2, 4, 8 or full page ? burst data transfer in sequential or interleaved order ? burst read with single write ? programmable cas latency: 2, 3 ? 8 column block write and write-per-bit modes ? independent byte operation via dqm 0..3 interface ? auto precharge and auto refresh modes ? 2k refresh cycles / 32 ms ? lvttl compatible i/o ? hidden autoprecharge for read bursts
HYB39S16320TQ-6 /-7 /-8 overview semiconductor group 6 1.1999 1.2 pin configuration figure 1 (top view)
semiconductor group 7 1.1999 HYB39S16320TQ-6 /-7 /-8 overview 1.3 pin definitions and functions table 1 clk clock input cke clock enable cs chip select ras row address strobe cas column address strobe we write enable a0-a9 address inputs a8 / ap auto precharge ba bank select dq 0 to dq 31 data input /output dqm 0 to dqm 3 data mask v dd power (+3.3v) v ss ground v ddq power for dqs (+ 3.3v) v ssq ground for dqs nc not connected dsf special function enable mch must connect high
HYB39S16320TQ-6 /-7 /-8 overview semiconductor group 8 1.1999 1.4 signal pin description pin type signal polarity function clk input pulse positiv edge the system clock input. all of the sgram inputs are sampled on the rising edge of the clock. cke input level active high activates the clk signal when high and deactivates the clk signal when low. by deactivating the clock, cke low initiates the power down mode, suspend mode, or the self refresh mode. cs input pulse active low cs enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras , cas we input pulse active low when sampled at the positive rising edge of the clock, cas , ras , and we define the operation to be executed by the sgram. a0 - a9 input level during a bank activate command cycle, a0-a9 defines the row address (ra0-ra9) when sampled at the rising clock edge. during a read or write command cycle, a0-a7 defines the column address (ca0-ca7) when sampled at the rising clock edge. in addition to the column address, ca8 is used to invoke autoprecharge operation at the end of the burst read or write cycle. if a8 is high, autoprecharge is selected and ba defines the bank to be precharged (low=bank a, high=bank b). if a8 is low, autoprecharge is disabled. during a precharge command cycle, a8 is used in conjunction with ba to control which bank(s) to precharge. if a8 is high, both bank a and bank b will be precharged regardless of the state of ba. if a8 is low, then ba is used to define which bank to precharge. ba input level selects which bank is activated. ba low selects bank a and ba high selects bank b. dq0- dq31 input/ output level data input/output pins operate in the same manner as on conventional drams, with the exception of the block write function. in this case, the dqx pins perform a masking operation. table continued on next page
HYB39S16320TQ-6 /-7 /-8 overview semiconductor group 9 1.1999 dqm0 - dqm3 input pulse during read, dqm = 1 turns off the output buffers. during write, dqm = 1 prevents a write to the current memory location. dqm0 corresponds to dq0 - dq7 dqm1 corresponds to dq8 - dq15 dqm2 corresponds to dq16 - dq23 dqm3 corresponds to dq24 - dq31 vdd, vss supply power and ground for the input buffers and the core logic. vddq vssq supply isolated power supply and ground for the output buffers to provide improved noise immunity. dsf input level dsf is part of the input command to the sgram. if dsf is low, sgram operates in the same way as sdrams.when dsf is high it enables the block write and masked write and special mode register setup cycle. pin type signal polarity function
HYB39S16320TQ-6 /-7 /-8 overview semiconductor group 10 1.1999 1.5 functional block diagrams figure 2 block diagram row decoder memory array bank 0 1024 x 256 x 32 bi t column decoder sense amplifier & i(o) bus row decoder memory array bank 1 1024 x 256 x 32 bi t input buffer output buffer dq0-dq31 column address counter column address buffer row address buffer refresh counter a0 - a7, ap, ba control logic & timing generator clk cke cs ras cas we dqmx row addresses column addresses a0 - a9, ba color register mask register dsf column decoder sense amplifier & i(o) bus
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HYB39S16320TQ-6 /-7 /-8 functional description semiconductor group 12 1.1999 2 functional description 2.1 general the 16mb sgram is a dual bank 1024 x 256 x 32 dram with graphics features of block write and masked write. it consists of two banks. each bank is organized as 1024 rows x 256 columns x 32 bits. read and write accesses are burst oriented. accesses begin with the registration of an activate command which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and the row to be accessed. ba selects the bank and address bits a9 -a0 select the row. address bits a7-a0 registered coincident with the read or write command are used to select the starting column location for the burst access. block writes are not burst oriented and always apply to eight column locations selected by a7-a3. dqs registered at block write command are used to mask the selected columns. dqs registered coincident with the load special mode register command are used as color data (lc bit =1) or persistent mask (lm = 1). if lc and lm are both 1 in the same load special mode register command cycle, the data of the mask and the color register will be unknown. 2.2 initialization the default power on state of the mode register is supplier specific and may be undefined. the following power on and initialization sequence guarantees, that the device is preconditioned to each users specific needs. the following sequence is recommended: ? during power on, all vdd and vddq pins must be built up simultaneously to the specified voltage when the input signals are held in the nop state. ? the power on voltage must not exceed vdd+0.3v on any of the input pins or vdd supplies. ? the clk signal must be started at the same time. ? after power on, an initial pause of 200 m s is required. ? the pause is followed by a precharge of both banks using the precharge command. ? to prevent data contention on the dq bus during power on, it is required that the dqm and cke pins be held high during the initial pause period. ? once all banks have been precharged, the mode register set command must be issued to initialize the mode register. ? a minimum of eight auto refresh cycles (cbr) are also required. it is also possible to reverse the last two steps of the initialization procedure: first send at least 8 cbr commands, then the lmr command. failure to follow these steps may lead to unpredictable start-up modes.
HYB39S16320TQ-6 /-7 /-8 functional description semiconductor group 13 1.1999 2.3 mode register programming the mode register is used to define: a burst length, a burst type, a read latency and an operating mode. the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device looses power.the mode register must be loaded when both banks are idle and the controller must wait the specified time before initiating the subsequent command. violating either of these requirements may result in unknown operation. 2.3.1 burst length read and write operations to the sgram are burst oriented, with the burst length being programmable. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types and a full page burst is available for the sequential type. the full page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. when a read or write command is issued, a block of columns equal to the burst length is selected. the block is defined by address bits a7-a1 when the burst length is set to 2, by a7-a2 for burst length set to 4 and by a7-a3 for burst length set to 8. the lower order bit(s) are used to select the starting location within the block. the burst will wrap within the block if a boundary is reached. 2.3.2 burst type accesses within a given burst may be programmed to be either sequential or interleaved and the type is selected based on the setting of bt bit in the mode register. if bt is set to 0, the burst type is sequential, if bt is 1, the burst type is interleave. 2.3.3 read latency the read latency is the delay in clock cycles between the registration of a read command and the availability of the first piece of output data. the latency can be set to 2 or 3 clocks. if a read command is registered at clock edge n and the read latency is 2 clocks, the data will be available by clock edge n+2. the dqs will start driving already one cycle earlier (n+1). 2.3.4 color register the siemens 16m sgram offers two color registers. if bit m7 is set to 1, two color register mode is specified.
HYB39S16320TQ-6 /-7 /-8 functional description semiconductor group 14 1.1999 2.3.5 operation mode in normal operation, the bits m8 and m9 of mode register (mr) are set 0. the programmed burst length applies to both read and write bursts. when bit m8 is set to 1, burst read and single write mode is selected. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. 2.4 load special mode register (lsmr) the special mode register command is used to load the mask and color registers, which are used in block write and masked write cycles.the data to be written to either the color registers or the mask register is applied to the dqs and the control information is applied to the address inputs. during a lsmr cycle, if the address bit a6 is 1, and all other address inputs are 0, the color register 0 will be loaded with the data on the dqs. if the address bits a6 and a7 are both set equal to 1 and mode register m7 bit was already set to 1, color register 1 will be loaded with the data on the dqs.this color data is used for block write cycles. similarly, when input a5 is 1, and all other address inputs are 0 during a lsmr cycle, the mask register will be loaded with the data on the dqs. never set bit a5 to 1 when a6 and/or a7 are set equal to 1 in the same load special mode register cycle to avoid unknown operation. 2.4.1 color registers two color registers (color register 0 and color register 1) are available in the devices. each color register is a 32-bit register which supplies the data during block write cycles. the color register is loaded via a load special mode register command, as shown in the function truth table and will retain data until loaded again with a new data or until power is removed from the sgram. 2.4.2 mask register the mask register (or the write-per-bit mask register) is a 32-bit register which acts as a per-bit mask during masked write and masked block write cycles. the mask register is loaded via the load special mode register command and will retain data until loaded again or until power is removed from the sgram.
HYB39S16320TQ-6 /-7 /-8 functional description semiconductor group 15 1.1999 2.5 commands the function truth table provides a quick reference of available commands. table 2 notes concerning special operation see next page function truth table operation cke n-1 cke n cs ras cas we dsf dqm ba a8 a0- a7 device deselect (inhbt) h x h x x x x x x x x no operation (nop) h x l h h h x x x x x load mode register (lmr) h x l l l l l x x opcode load special mode register (lsmr) hxllllhxxopcode row activate (act) h x l l h h l x ba row addr row active with wpb (actm) h x l l h h h x ba row addr read (rd) h x l h l h x x ba l col. read with auto precharge (rda) hxlhlhx xbahcol. write command (wr) h x l h l l l x ba l col. write command with auto precharge (wra) h x l h l l l x ba h col. block write (bw) h x l h l l h x ba l col. block write with auto precharge (bwa) h x l h l l h x ba h col. burst terminate (bst) h x l h h l x x x x x precharge single bank (pre) hxl lhlx xbalx precharge all banks (preal) hxl lhlx x xhx auto refresh (ref) h h l l l h x x x x x self refresh entry (sref(en)) hllllhxxxxx self refresh exit (sref(ex)) l l h h h l x h x h x h x x x x x x x x x x power down mode entry (pdn-en) h h l l h l x h x h x h x x x x x x x x x x power down mode exit (pdn-ex) lhxxxxx x xxx
HYB39S16320TQ-6 /-7 /-8 functional description semiconductor group 16 1.1999 note 01 all inputs are latched on the rising edge of the clk. note 02 lmr, ref and sref commands should be issued only after both banks are deactivated (preal command). note 03. act and actm command should be issued only after the corresponding bank has been deactivated (pre command). note 04. wr, wra, rd, rda should be issued after the corresponding bank has been activated (act command). note 05. auto precharge command is not valid for full-page burst. note 06. bw and bwa commands use mask register data only after actm command. dqm byte masking is active regardless of wpb mask. note 07. loading mask register: initiate an lsmr cycle with address pin a5 =1 to load the mask register with the mask data present on dq pins. except a5 , all other address pins must be 0 during lsmr cycle while loading the mask register note 08. loading color register: initiate an lsmr cycle with address pin a6 =1 to load the color register with the color input data on dq pins. address pin a7 selects color register. except a6 and a7 , all other address pins must be 0 during lsmr cycle while loading a color register. if one color register mode is enabled, all address pins, except a6, must be 0 during lsmr cycle. note 09. if bw or bwa operation is initiated and 2-color register mode is initialized by the mode register, address a0 selects the desired color register for the operation. if a0 = 0, color register 0 will be used, if a0 = 1, color register 1. note 010. any write or block write cycles to the selected bank/row while active will be masked according to the contents of the mask register, in addition to the dqm signals and the column/byte mask information (the later for block writes only). note 011. block writes are not burst oriented and always apply to the eight column locations selected by a7-a3 . note 012. addressline a9 is always x with the exception of two commands: in lmr and lsmr commands it provides opcode (see description mode and special mode register) in act and actm commands it provides the addressbit 9 of the row address.
HYB39S16320TQ-6 /-7 /-8 functional description semiconductor group 17 1.1999 2.5.1 address input for mode set (mode register functions) figure 3 a3 a4 a2 a1 a0 a9 a8 a7 a6 a5 address bus (ax) bt burst length cas latency mode register (mx) cas latency m6 m5 m4 latency 0 0 0 reserved 0 0 1 reserved 010 2 011 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved burst length m2 m1 m0 length sequential interleave 000 1 1 001 2 2 010 4 4 011 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved burst type m3 type 0 sequential 1 interleave operation mode m9 m8 mode 0 0 normal 01 multiple burst with single write write mode cr color register m7 registers 0 one color register 1 two color register
HYB39S16320TQ-6 /-7 /-8 functional description semiconductor group 18 1.1999 2.5.2 burst length and sequence: table 3 table 4 table 5 burst of two starting address (column address a0) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 0 0, 1 0, 1 1 1, 0 1,0 burst of four starting address (column address a1 - a0) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 0 0, 1,2,3 0, 1, 2, 3 1 1, 2, 3, 0 1, 0, 3, 2 2 2, 3, 0 , 1 2, 3, 0 ,1 3 3, 0, 1 , 2 3, 2, 1, 0 burst of eight starting address (column address a1 - a0) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 0 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 1 1,2,3,4,5,6,7,0 1,0,3,2,5,4,7,6 2 2,3,4,5,6,7,0,1 2,3,0,1,6,7,4,5 3 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4 4 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 5 5,6,7,0,1,2,3,4 5,4,7,6,1,0,3,2 6 6,7,0,1,2,3,4,5 6,7,4,5,2,3,0,1 7 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0 full page burst full page burst is an extension of the above tables of sequential addressing with the burst length being 256.
HYB39S16320TQ-6 /-7 /-8 functional description semiconductor group 19 1.1999 2.5.3 special mode register functions: table 6 note: if only one color register is in use, a7 is dont care. table 7 2.5.4 device deselect (inhbt) the device deselect or inhibit function prevents commands from being executed by the sgram, regardless of whether the clk signal is enabled. the device is effectively deactivated (cs is high). 2.5.5 no operation (nop) the nop command is used to perform a no operation to an sgram which is selected (cs is low). this prevents unwanted commands being registered during idle or wait states. the execution of the command(s) already in progress will not be affected 2.5.6 load mode register (lmr) the mode register is loaded via address input pins a9 - a0 . the lmr command can only be issued when both banks are idle, and a subsequent executable command can not be issued until 2 clk cycle latency is met. address bits functions a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000100000 load mask register 0001000000 load color register 0 0011000000 load color register 1 special mode register naming conventions address bit name special name function a5 lm load mask enable a6 lc load color enable a7 scr select color register
HYB39S16320TQ-6 /-7 /-8 functional description semiconductor group 20 1.1999 2.5.7 load special mode register (lsmr) lsmr command is used to load either the color register(s) or the mask register at a time. the control information is provided on inputs a9 - a0 , while the data for the color or mask register is provided on the dqs. the lsmr command can be issued when both banks are idle, or one or both are active but with no read, write or block write accesses in progress. 2.5.8 active (act) the act command is used to open (or activate) a row in a particular bank. the value on ba selects the bank and the address provided on input pins a9 - a0 selects the row. this row remains open for accesses until a precharge command is issued to the bank. a precharge command must be issued before opening a different row in the same bank. 2.5.9 active with wpb (actm) actm command is similar to the act command, except that the write-per-bit mask is activated. any write or block write cycles to the selected bank/row while active will be masked according to the contents of the mask register. 2.5.10 read (rd) the read command is used to initiate a burst read access from an active row. the value on ba selects the bank and the address provided on inputs a7 - a0 selects the starting column location. the value on a8 determines whether or not auto precharge is used. if a8 is 1, auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. if a particular dqm was registered high, the corresponding dqs appearing 2 clocks later on the output pins will be high-z. 2.5.11 write (wr) the write command is used to initiate a burst write access to an active row. the value on ba selects the bank and the address provided on inputs a7 -a0 selects the starting column location. the value on a8 determines whether or not auto precharge is used. if a8 is 1, auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. if a particular dqm is registered high, the corresponding data inputs will be ignored and the write will not be executed to that byte location.
HYB39S16320TQ-6 /-7 /-8 functional description semiconductor group 21 1.1999 2.5.12 block write (bw) the block write command is used to write a single data value to the block of eight consecutive column locations addressed by inputs a7 - a3 . the data is provided by the color register which must be loaded prior to the block write cycle by invoking lsmr cycle. if the two color register option is enabled, the address line a0 is used to select the desired color register. a 0 at a0 selects color register 0, a 1 color register 1. the input data on dqs which is registered coincident with the block write command is used to mask specific column/byte combinations within the block. the dqm signals operate the same way as for write cycles, but are applied to all eight columns in the selected block. 2.5.13 precharge (pre) the precharge command is used to deactivate the open row in a particular bank or the open row in both banks. the bank(s) will be available for row access some specified time (trp) after the precharge command is issued. input a8 determines whether one or both banks are to be precharged, input ba selects the bank. if a8 is 1, both banks are to be precharged and ba is don't care. once a bank is precharged (or deactivated), it is in the idle state and must be activated prior to any read, write, or block write commands being issued to that bank. 2.5.14 auto precharge (prea) the auto precharge feature allows the user to issue a read, write, or block write command that automatically performs a precharge upon the completion of the block write access or read or write burst, except in the full page burst mode, where it has no effect. the use of this feature eliminates the need to manually issue a precharge command during the functional operation of the sgram. 2.5.15 burst terminate (bst) the burst terminate command is used to truncate either fixed-length or full page bursts. 2.5.16 auto refresh (ref) auto refresh is used to refresh the various rows in the sgram and is analogous to cas-before- ras (cbr) in drams. this command must be issued each time a refresh is required. the addressing is generated by the internal refresh counter, therefore, the address bits are don't care during a cbr cycle. the sgram requires that 2048 rows to be refreshed every 32ms (t ref ). this refresh can be accomplished either by providing a auto refresh command every 15.6s or all 2048 auto refresh commands can be issued in a burst at the minimum cycle rate (trc) once every 32ms.
HYB39S16320TQ-6 /-7 /-8 functional description semiconductor group 22 1.1999 2.5.17 self refresh (sref) the self refresh command can be used to retain data in the sgram, even if the rest of the system is powered down. when in the self refresh mode, the sgram retains data without external clocking. once the sref command is registered, all the inputs to the sgram become don't care with the exception of cke, which must remain low. once sref mode is engaged, the sgram provides its own internal clocking, causing it to perform its own auto refresh cycles. the sgram may remain in self refresh mode for an indefinite period. the procedure for exiting requires a sequence of commands. first, the system clock must be stable prior to cke going high. once cke is high, the sgram must have nop commands issued for t srx , because of the time required for the completion of any bank currently being internally refreshed.
HYB39S16320TQ-6 /-7 /-8 functional description semiconductor group 23 1.1999 2.6 detailed description of write commands (wr, masked writes, block write) 2.6.1 write command (wr) the following pages illustrate the write operations for various cases table 8 note: input data at dq pins at block write command is registed as a column mask for that block of columns note: explanation of mnemonics: wr: write command wra: write command with auto precharge bw: block write bwa: block write with auto precharge ba: bank select write bursts are initiated with a write command. the starting column and bank address is provided with the write command, normal or block write is selected, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged automatically at the completion of the burst. during write bursts, the first valid data-in element will be registered coincident with the write command. sub-sequent data elements will be registered on successive positive clock edge. upon completion of a fixed-length burst, assuming no other commands have been initiated, the dqs will remain high-z, and any additional data will be ignored. a full-page burst will continue until terminated (at the end of the page, it will wrap to column 0 and continue). a fixed-length write burst may be followed by, or truncated with a subsequent write burst or block write command (provided that auto precharge was not activated) and a full page write burst can be truncated with a subsequent write burst or block write command. the new write or block write command can be issued on any clock following the previous write command, and the data provided coincident with the new command applies to the new command. to truncate a block write, the t bwc parameter has to be met. summary write commands mnemonic cke cs ras cas we dsf dqm ba a8 address lines wr h l h l l l 0 ba l column wra h l h l l l 0 ba h column bw h l h l l h 0 ba l column bwa h l h l l h 0 ba h column
HYB39S16320TQ-6 /-7 /-8 functional description semiconductor group 24 1.1999 a fixed-length write burst may be followed by, or truncated with a subsequent read burst (provided that auto precharge was not activated) and a full-page write burst can be truncated with a subsequent read burst. once the read command is registered, the data inputs will be ignored, and writes will not be executed. a fixed-length write burst may be followed by, or truncated with a precharge command to the same bank (provided that auto precharge was not activated) and a full-page write burst may be truncated with a pre-charge command to the same bank. the precharge command should be issued x cycles (x = t wr /t ck rounded up to the next whole number) after the clock edge at which the last desired input data element is registered. in addition, the dqm signals must be used to mask input data, starting with the clock edge following the last desired data element and ending with the clock edge on which the precharge command is entered. a precharge command issued at the optimum time provides the same operation that would result from the same fixed-length burst with auto precharge.
HYB39S16320TQ-6 /-7 /-8 functional description semiconductor group 25 1.1999 2.6.2 disadvantages of write command with auto precharge 1. back to back read/write bursts can not be initiated. the read/write command with auto precharge will automatically initiate a precharge of the row in the selected bank. most of the applications require subsequent read/write bursts in the same page. 2. the auto precharge command does not allow truncation of fixed-length bursts. it also does not apply to full page bursts. 2.6.3 terminating a write burst the fixed-length or full-page write bursts can be truncated with the burst terminate command. when truncating a write burst, the input data applied one clock edge prior to the burst terminate command will be the last data written. 2.6.4 masked writes any write performed to a row that was activated via an active with wpb command is a write-per- bit-mask (wpbm). data is written to the 32 cells at the selected column location subject to the mask stored in the wpb mask register. the data to be written in the dram cell will be according to the following mask: table 9 symbolic representation of write masking function figure 4 write masking function representation dqm mr dram cell 00mask 10mask 11mask 01write mr dqm dram cell dq
HYB39S16320TQ-6 /-7 /-8 functional description semiconductor group 26 1.1999 if a particular bit in the wpb mask register is a 0, the data appearing on the corresponding dq input will be ignored, and the existing data in the corresponding dram cell will remain unchanged. if a mask data is a 1, the data appearing on the corresponding dq input will be written to the corresponding dram cell. the overall write mask consists of a combination of the dqm inputs, which will mask on a per-byte basis, and the wpb mask register, which masks on a per-bit basis. if a particular dqm signal was registered high, the corresponding byte will be masked. a given bit is written if the corresponding dqm signal registered is 0and the corresponding wpb mask register bit is 1. note that the dqm latency for write is zero. 2.6.5 block write (bw) each block write cycle writes a single data value from a color register to the block of eight consecutive column locations addressed by a 7 - a 3 . if single color register mode is enabled, the content of color register 0 is written. if both color registers are enabled, address pin a0 selects the desired color register. address a0 = 0 selects color register 0, address pin a0 = 1 color register 1. the information on the dqs which is registered coincident with the block write command is used to mask specific column/byte combinations within the block. table 10 the table shows the masking of data caused by the registered value on the dq pins, when data is transfered from color register to the 8 succeeding memory locations addressed in the write block command. when a 1 is registered, the color register data will be written to the corresponding dram cells, subject to the dqm and the wpb masking. the overall block write mask consists of a combination of the dqm signals, the wpb mask register and the column/byte mask information. bit mask mapping of dq bits address within written block byte within data word byte 3 byte 2 byte 1 byte 0 0 dq24 dq16 dq8 dq0 1 dq25 dq17 dq9 dq1 2 dq26 dq18 dq10 dq2 3 dq27 dq19 dq011 dq3 4 dq28 dq20 dq12 dq4 5 dq29 dq21 dq13 dq5 6 dq30 dq22 dq14 dq6 7 dq31 dq23 dq15 dq7
HYB39S16320TQ-6 /-7 /-8 functional description semiconductor group 27 1.1999 2.6.6 block write timing considerations. a block write access requires a time period of t bwc to execute, so in general, the cycle after the block write command should be a nop. however, active or precharge commands to the other bank are allowed. when following a block write with a precharge command to the same bank, t bpl must be met. block write illustration: note: only single color register and byte 0 of color register is used in this example. i i+1 i+2 i+3 i+4 i+5 i+6 i+7 color register color data write data mask write, keep original data write-per-bit mask data = mask register + dqmi mask register mdq7 - mdq0 01001011 dq0 = 1 mdq0 = 1 dq1 = 1 mdq1 = 1 dq2 = 1 mdq2 = 0 dq3 = 0 mdq3 = 1 dq4 = 0 mdq4 = 0 dq5 = 1 mdq5 = 0 dq6 = 1 mdq6 = 1 dq7 = 0 mdq7 = 0 column address mask from dq pins c olumn address
HYB39S16320TQ-6 /-7 /-8 electrical characteristic semiconductor group 28 1.1999 3 electrical characteristic 3.1 absolute maximum ratings operating temperature range......................................................................................... 0 to + 70 c storage temperature range..................................................................................... C 55 to + 150 c input/output voltage .......................................................................................... C 0.3 to v dd + 0.3 v power supply voltage v dd / v ddq ............................................................................ C 0.3 to + 4.6 v power dissipation .............................................................................................................. ......... 1 w data out current (short circuit) ............................................................................................... . 50 ma note: stresses above those listed under absolute maximum ratings may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
HYB39S16320TQ-6 /-7 /-8 electrical characteristic semiconductor group 29 1.1999 table 11 note: 1) t a = 0 to 70 c; v ss = 0 v; v dd, v ddq = 3.3 v 0.3 v 2) all voltages are referenced to v ss 3) v ih may overshoot to v dd + 2.0v for pulse width of <4ns with 3.3v. v il may undershoot to -2.0v for pulse width <4ns with 3.3v. pulse width measured at 50% points with amplitude measured peak to dc reference. table 12 note: t a = 0 to 70 c; v dd = 3.3 v 0.3 v, f = 1 mhz recommended operation and dc characteristics parameter symbol limit values unit notes min. max. input high voltage v i h 2.0 v dd +0.3 v 2, 3 input low voltage v i l C 0.3 0.8 v 2, 3 output high voltage ( i out = C 2.0 ma) v oh 2.4 C v output low voltage ( i out = 2.0 ma) v ol C0.4v input leakage current, any input (0 v < v i n < 3.6 v, all other inputs = 0 v) i i (l) C 5 5 m a output leakage current (dq is disabled, 0 v < v out < v dd ) i o(l) C 5 5 m a capacitance parameter symbol max. values unit input capacitance (a0 to a9,ba) c i 1 4pf input capacitance (ras , cas , we , cs , clk, cke, dqm,dsf) c i 2 4pf output capacitance (dq) c i o 6pf
HYB39S16320TQ-6 /-7 /-8 electrical characteristic semiconductor group 30 1.1999 3.2 operating currents table 13 notes see next page operating currents table parameter sym- bol test condition cas latency -6 - 7 - 8 unit note max. operating current icc1 trc>=trc (min.) tck>=tck(min.), io = 0ma 3 200 200 180 ma 4 2 180 180 170 precharge standby current in power down mode i cc2 p cke<=vil(max), tck=tck(min.) 3 3 3 ma 4 i cc2 ps cke<=vil(max), tck=infinite 2 2 2 ma precharge standby current in non- power down mode i cc2 n cke>=vih(min), tck>=tck(min.), input changed once in 30 ns 60 60 60 ma 4 i cc2 ns cke>=vih(min), tck=infinite, no input change 15 15 15 ma active standby current in power down mode i cc3 p cke<=vil(max), tck>=tck(min.) 666 ma i cc3 ps cke<=vil(max), tck=infinite 6 6 6 active standby current in non-power down mode i cc3 n cke>=vih(min), tck>=tck(min.) input changed every 30 ns 90 90 90 ma i cc3 ns cke>=vih(min),tck=infinite, no input change 30 30 25 burst operating current i cc4 burst length = full page trc = infinite, tck >= tck(min.), io = 0 ma 2 banks interleave 3 200 200 190 ma 4, 5 2 200 200 190 auto (cbr) refresh current i cc5 trc>=trc(min) 3 170 170 160 ma 4 2 160 160 160 self refresh current i cc6 cke=<0,2v 2 2 2 ma operating current (block write) icc7 tck >= tck (min.), io = 0 ma tbwc = tbwc(min.) 200 200 190 ma
HYB39S16320TQ-6 /-7 /-8 electrical characteristic semiconductor group 31 1.1999 note: 1) ta = 0 to 70 c, v dd = 3.3v 0.3v 2) these are recommended operating conditions unless otherwise noted 3) all values are preliminary and subject to future change 4) these parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t ck and t rc . input signals are changed one time during t ck . 5) these parameters depend on output loading. specified values are obtained with output open.
HYB39S16320TQ-6 /-7 /-8 electrical characteristic semiconductor group 32 1.1999 3.3 ac characteristics parameter cas la- tency sym- bol limit values unit note - 6- 7- 8 minmaxminmaxminmax clock and clock enable clock cycle time 3 t ck3 678ns 2 t ck2 8 8 10 ns system frequency 3 166 143 125 mhz 2 125 125 100 mhz clock access time (for 30 pf load) 3 t ac3 5.5 5.5 6 ns 3 2 t ac2 5.5 5.5 6 ns 3 clock high pulse width t ch 2.5 C3C3Cns clock low pulse width t cl 2.5 C 2.5 C 3 C ns cke setup time t cks 2C2C2.5Cns cke hold time t ckh 1C1C1Cns transition time (rise and fall) t t 0.5 10 0.5 10 0.5 10 ns common parameters command setup time t cs 2C2C2.5Cns4 command hold time t ch 1C1C1Cns address setup time t as 2C2C2.5Cns4 address hold time t ah 1.3 C 1.3 C 1.3 C ns active to read or write delay t rcd 18 C 21 C 24 C ns 5 cycle time t rc 66 C 70 C 80 C ns 5 active to precharge command period t ras 48 100k 49 100k 56 100k ns 5 row precharge time t rp 18 C 21 C 24 C ns 5 active bank a to active bank b command period t rrd 12 C 14 C 16 C ns 5 cas to cas delay time (same bank) t ccd 1C1C1Cclk table continued on next page.
HYB39S16320TQ-6 /-7 /-8 electrical characteristic semiconductor group 33 1.1999 table 14 notes see next page refresh cycle self refresh exit time t srex 2 C2C2Cclk6 total self refresh exit time 2 clks + t rc 2 clks + t rc 6 refresh period for non-self refresh t ref C32C32C32ms7 read cycle data out hold time t oh 2.5 C 2.5 C 3 C ns data out to low impedance time t lz 0C0C0Cns data out to high impedance time t hz 383838ns8 write cycle data in setup time t ds 2C2C2.5Cns data in hold time t dh 1C1C1Cns write recovery time t wr 6C7C8Cns block write cycle block write cycle time t bwc 12 C 14 C 16 C ns block write to precharge delay t bwr 12 C 14 C 16 C ns miscellaneous mode register command to command t rsc 2C2C2Cclk parameter cas la- tency sym- bol limit values unit note - 6- 7- 8 minmaxminmaxminmax
HYB39S16320TQ-6 /-7 /-8 electrical characteristic semiconductor group 34 1.1999 note: 1) t a = 0 to 70 c; v ss = 0 v; v dd = 3.3 v 0.3 v, t t = 1 ns 2) ac timing tests have v il = 0.4v and v ih = 2.4v with the timing referenced to the 1.4 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t =1ns with the ac output load circuit shown note: 3) if clock rising time is longer than 1ns, a time (t t /2 - 0.5)ns has to be added to this parameter. 4) if tt is longer than 1ns, a time (t t - 1)ns has to be added to this parameter. 5) these parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: number of clock cycle = specified value of timing period (counted in fractions as a whole number) 6) self refresh exit is a synchronous operation and begins on the second positiv edge after cke returns high. self refresh exit is not complete until a time period equal to t rc is satisfied once the self refresh exit command is registered. 7) any time that the refresh period has been exceeded, a minimum of two auto (crb) refresh commands must be given to wake-up the device. 8) referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 1.4v 1.4v t setup t hold t ac t ac t lz t oh t hz clock input output 30 pf i/o z=50 ohm + 1.4 v 50 ohm 2.4v 0.4v t t dout t oh t ch
HYB39S16320TQ-6 /-7 /-8 electrical characteristic semiconductor group 35 1.1999 3.4 clock frequency and latency table 15 parameter symbol speed sort unit - 6 - 7 - 8 clock frequency max. 166 125 143 125 125 mhz clock cycle time min. t ck 68788ns cas latency min. t aa 32323clk ras to cas delay min. t rcd 33333clk bank active cycle time min. t ras 86767clk bank active cycle time max. t ras 100 100 100 100 100 m s precharge time min. t rp 33333clk bank cycle time min. t rc 11910910clk last data in to precharge min. t wr 11111clk last data in to active/ refresh min. t wr + t rp 44444clk bank to bank delay time min. t rrd 2 22 22clk cas to cas delay time min. t ccd 11111clk write latency fixed t wl 00000clk dqm write mask latency fixed t dqw 00000clk dqm data disable latency fixed t dqz 22222clk clock suspend latency fixed t csl 11111clk block write cycle time fixed t bwc 22222clk
HYB39S16320TQ-6 /-7 /-8 package outlines semiconductor group 36 1.1999 all dimensions in millimeters pin 1 i.d. 1.60 max 0.60 + 0.15/-0.15 lead coplanarity seating plane 0.10 max rad 0.08 min 0 - 7 1.40. 0.05 0.05/0.15 (min/max) 1.60 max 0.65 basic 0.22 - 0.35 20.00 . 0.20 22.00 . 0.20 14.00 . 0.20 16.00 . 0.20 30 50 80 100 + - + - + - + - + - o 12 typ. o 12 typ. conforms to jedec ms-026 bha rad 0.20 max 4 package outlines plastic package tqfp-100 (20x14mm2, 0.65mm lead pitch) thin small outline package, smd
HYB39S16320TQ-6 /-7 /-8 package outlines semiconductor group 37 1.1999

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